This invention relates to a pattern lithography system for fabrication of a mask, a wafer or the like for production of semiconductor devices, and more particularly to a pattern lithography system having the capability of shifting a deflection boundary or varying a field size.
In recent years, pattern lithography systems using an electron beam have been used to form semiconductor integrated circuit patterns on a resist coated on a semiconductor substrate such as a mask, a wafer or the like. The lithography system deflects the electron beam by an electromagnetic means so as to irradiate the electron beam onto a desired position on the semiconductor substrate. In the case where the deflection is carried out in a wide area, an error due to aberration or the like increases so as to produce a deflection distortion in the lithographed pattern. Therefore, the size of the area in which the deflection can be carried out is often limited to about several millimeters so that accuracy on the deflection boundary or pattern position accuracy is less than an allowed value.
Further, in order to realize this kind of system capable of lithographing the pattern with high precision and high throughput, a multiple stage deflector such as a two-stage deflector having a main and an auxiliary deflector, or a three-stage deflector having a main, an auxiliary and a sub-auxiliary deflector, has been widely used. Generally, because the semiconductor integrated circuit is so large that it cannot be set within the deflection area of the pattern lithography system, an entire circuit pattern is divided into a plurality of areas capable of being deflected and the entire circuit pattern is lithographed by separately lithographing each area respectively.
On the other hand, in recent years, because the semiconductor integrated circuit has been becoming smaller, a method for higher precision in pattern lithography has been demanded. As one of the methods for realizing such a high precision pattern lithography, so-called `multiple lithography` has been recently proposed. By lithographing the same area in a pattern repeatedly, accuracy on the deflection boundary and pattern position accuracy which cannot be improved even if the deflection area is contained within a certain size can be improved through an averaging effect.
However, according to this method, a plurality of overlapped lithography data each having a shifted deflection boundary must be prepared. Therefore, problems which increase both a data conversion time and a data amount for pattern lithography are inevitable. Generally, it takes an extremely large calculation time to convert the pattern data for a semiconductor circuit produced by CAD (Computer-Aided Design) or the like to data which can be input to the pattern lithography system. By producing data for n overlapping areas, for example, the calculation time required for this data conversion increases by n times as well as the data amount for pattern lithography.
In recent years, the scale of the semiconductor integrated circuit has become larger and larger, and the data amount for pattern lithography increases in a straight line with this growth. Further, the development and production of logic semiconductor circuits that include a memory circuit, and a new technique called `photo proximity effect correction` proposed recently, have further accelerated the increase of the data amount required for pattern lithography.
Generally, enlargements of a data processing computer and a recording medium such as a magnetic recording apparatus are necessary due to an increase of the lithography data amount. These enlargements further increase a data processing time, a data I/O amount, a lithography data transportation time through network and the like as well as an investment for semiconductor production. These reduce productivity of the semiconductor production. All prior art systems to date have required the preparation and storage in the lithography system of all lithography data for an entire wafer before the lithography process can begin. Therefore, the increase of the lithography data amount leads to an increase of production cost for the semiconductor integrated circuit. In the case when the lithography data amount increases greatly, the pattern lithography itself may be almost impossible because there is not sufficient memory space to store the lithography data in the recording medium or pattern memory of the pattern lithography system. Therefore, compression of the lithography data amount is one of the most important problems for production of the semiconductor integrated circuit.
As described above, in the case where multiple lithography is carried out with a shifted deflection boundary, the lithography data amount is greatly increased. Such an increase of the lithography data amount then requires enlargement of the data processing computer and the recording medium, thereby leading to an increase of the data processing time, the lithography data transportation time and the like as well as the investment for semiconductor production. Ultimately, the productivity of semiconductor production drops, thereby leading to a rise of production cost on the semiconductor integrated circuit.
The above problems also exist in not only pattern lithography systems that use an electron beam, but also in systems that use an ion beam or a laser beam.